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Test
The Test Access Port interface is controlled via five dedicated pins. These pins are described in
Table
9-1.
Table 9-1. TAP Controller Pin Definitions
Signal Name
Test Clock
Test Mode Select
Test Data In
Test Data Out
Asynchronous Reset
9.2
Reset
The boundary-scan interface includes a synchronous finite state machine, the TAP controller in
Figure 9-1. In order to force the TAP controller into the correct state, a reset pulse must be applied
to the nTRST pin.
Note: A clock on TCK is not necessary to reset the application processor.
To use the boundary-scan interface these points apply:
•
During power-up only, drive nTRST from low to high either before or at the same time as
nRESET.
•
During power-up only, wait 10 µs after deassertion of nTRST before proceeding with any
JTAG operation.
•
Always drive the nBATT_FAULT and nVDD_FAULT pins high. An active low signal on
either pin puts the device into sleep which powers down all JTAG circuitry.
The action of reset (either a pulse or a dc level) is:
•
System mode is selected (the boundary-scan chain does NOT intercept any of the signals
passing between the pads and the core.)
•
Idcode instruction is selected. If TCK is pulsed, the contents of the ID register are clocked out
of TDO.
If the boundary-scan interface is not to be used, then the nTRST pin may be tied permanently low
or to the nRESET pin.
9-2
Mnemonic
Type
Clock input for the TAP controller, instruction register, and test
TCK
Input
data registers.
Controls operation of the TAP controller. The TMS input is
TMS
Input
pulled high when not being driven. TMS is sampled on the
rising edge of TCK.
Serial data input to the instruction and test data registers. Data
TDI
Input
at TDI is sampled on the rising edge of TCK. TDI is pulled high
when not being driven.
Serial data output. Data at TDO is clocked out on the falling
edge of TCK. It provides an inactive (high-Z) state during non-
TDO
Output
shift operations to support parallel connection of TDO outputs
at the board or module level.
Provides asynchronous initialization of the JTAG test logic.
Assertion of this pin puts the TAP controller in the
nTRST
Input
Test_Logic_Reset state. An external source must drive this
signal from low to high for TAP controller operation.
Definition
Intel® XScale™ Microarchitecture User's Manual
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