Register 9: Cache Lock Down - Intel PXA255 User Manual

Table 7-13. TLB Functions
Invalidate I&D TLB
Invalidate I TLB
Invalidate I TLB entry
Invalidate D TLB
Invalidate D TLB entry
7.2.9

Register 9: Cache Lock Down

Register 9 is used for locking down entries into the instruction cache and data cache. (The protocol
for locking down entries can be found in
mini-data cache.
Table 7-14
and data TLB. The cache entry to lock is specified by the virtual address in Rd. The data cache
locking mechanism follows a different procedure than the instruction cache. The data cache is
placed in lock down mode such that all subsequent fills to the data cache result in that line being
locked in, as controlled by
Lock/unlock operations on a disabled cache have an undefined effect. This register is write-only.
Reads from this register, as with an MRC, have an undefined effect.
Table 7-14. Cache Lockdown Functions
Fetch and Lock I cache line
Unlock Instruction cache
Read data cache lock register
Write data cache lock register
Unlock Data Cache
Table 7-15. Data Cache Lock Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: writable bits set to 0
Bits
31:1
0
Intel® XScale™ Microarchitecture User's Manual
Function opcode_2
0b000
0b000
0b001
0b000
0b001
shows the command for locking down entries in the instruction cache, instruction TLB,
Table 7-15.
Function opcode_2
0b000
0b001
0b000
0b000
0b001
Access
Read-unpredictable / Write-as-Zero
Read-unpredictable / Write
CRm Data
0b0111 Ignored
0b0101 Ignored
0b0101 MVA
0b0110 Ignored
0b0110 MVA
Chapter 6, "Data Cache".) Data can not be locked into the
CRm Data
0b0001 MVA
0b0001 Ignored
Read lock mode
0b0010
value
Set/Clear lock
0b0010
mode
0b0010 Ignored
Reserved
Data Cache Lock Mode (L)
0 = No locking occurs
1 = Any fill into the data cache while this bit is set gets
locked in
Configuration
Instruction
MCR p15, 0, Rd, c8, c7, 0
MCR p15, 0, Rd, c8, c5, 0
MCR p15, 0, Rd, c8, c5, 1
MCR p15, 0, Rd, c8, c6, 0
MCR p15, 0, Rd, c8, c6, 1
Instruction
MCR p15, 0, Rd, c9, c1, 0
MCR p15, 0, Rd, c9, c1, 1
MRC p15, 0, Rd, c9, c2, 0
MCR p15, 0, Rd, c9, c2, 0
MCR p15, 0, Rd, c9, c2, 1
8 7 6 5 4 3 2
Description
1 0
L
7-11