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Lines are locked into a set starting at way 0 and may progress up to way 27; which set a line gets
locked into depends on the set index of the virtual address of the request.
Effect on Round Robin Replacement"
cache along with how the round-robin pointer is affected.
Figure 6-3. Locked Line Effect on Round Robin Replacement
Software can lock down data located at different memory locations. This may cause some sets to
have more locked lines than others as shown in
Lines are unlocked in the data cache by performing an unlock operation. See
"Register 9: Cache Lock Down" on page 7-11
the data cache.
Before locking, the programmer must ensure that no part of the target data range is already resident
in the cache. The Intel® XScale™ core will not refetch such data, which will result in it not being
locked into the cache. If there is any doubt as to the location of the targeted memory data, the cache
should be cleaned and invalidated to prevent this scenario. If the cache contains a locked region
which the programmer wishes to lock again, then the cache must be unlocked before being cleaned
and invalidated.
6.5
Write Buffer/Fill Buffer Operation and Control
The write buffer is always enabled which means stores to external memory will be buffered. The K
bit in the Auxiliary Control Register (CP15, register 1) is a global enable/disable for allowing
coalescing in the write buffer. When this bit disables coalescing, no coalescing will occur
regardless of the value of the page attributes. If this bit enables coalescing, the page attributes X, C,
and B are examined to see if coalescing is enabled for each region of memory.
Coalescing means that memory writes which occur with the same 16-byte aligned memory region
can become one burst to external memory rather than distinct bus cycles. Merges can match with
any write buffer entry, but they need to form contiguous data areas to coalesce. Byte writes may
coalesce into halfwords, halfwords into words, or words into a multi-word burst to external
memory. The Write Buffer attempts to replace distinct writes with burst writes to memory, greatly
improving write performance to burst memory devices such as SDRAM.
Intel® XScale™ Microarchitecture User's Manual
is an example of where lines of data may be locked into the
set 0: 8 ways locked, 24 ways available for round robin replacement
set 1: 23 ways locked, 9 ways available for round robin replacement
set 2: 28 ways locked, only ways 28-31 available for replacement
set 31: all 32 ways available for round robin replacement
set 0
set 1
way 0
way 1
way 7
way 8
way 22
way 23
way 30
way 31
...
set 2
Figure
6-3.
for more information about locking and unlocking
Data Cache
Figure 6-3, "Locked Line
set 31
Section 7.2.9,
6-13
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