Table of Contents
Advertisement
Software Debug
Figure 10-5. DBGRX Data Register
10.10.6.3
DBG.RR
The debugger uses DBG.RR as part of the synchronization that occurs between the debugger and
debug handler for accessing RX. This bit contains the value of TXRXCTRL[31] after a
Capture_DR. The debug handler automatically sets TXRXCTRL[31] by doing a write to RX.
The debugger polls DBG.RR to determine when the handler has read the previous data from RX.
The debugger sets TXRXCTRL[31] by setting the DBG.V bit.
10.10.6.4
DBG.V
The debugger sets this bit to indicate the data scanned into DBG_SR[34:3] is valid data to write to
RX. DBG.V is an input to the RX Write Logic and is also cleared by the RX Write Logic.
When this bit is set, the data scanned into the DBG_SR will be written to RX following an
Update_DR. If DBG.V is not set and the debugger does an Update_DR, RX will be unchanged.
This bit does not affect the actions of DBG.FLUSH or DBG.D.
10.10.6.5
DBG.RX
DBG.RX is written into the RX register based on the output of the RX Write Logic. Any data that
needs to be sent from the debugger to the processor must be loaded into DBG.RX with DBG.V set
to 1. DBG.RX is loaded from DBG_SR[34:3] when the JTAG enters the Update_DR state.
10-22
0
DBG_SR
TDI
35
34
cleared by
RX Write Logic
DBG_REG
34
33
TCK
RX
TXRXCTRL[31]
1
0
3
2
1
0
2
1
Intel® XScale™ Microarchitecture User's Manual
Capture_DR
0
TDO
DBG.RR
Update_DR
DBG.FLUSH
DBG.D
DBG.RX
DBG.V
Advertisement
Table of Contents
