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7.2.6
Register 6: Fault Address Register
Table 7-11. Fault Address Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: unpredictable
Bits
31:0
7.2.7
Register 7: Cache Functions
All the cache functions defined in existing StrongARM* products appear here. The Intel®
XScale™ core adds other functions as well. This register is write-only. Reads from this register, as
with an MRC, have an undefined effect.
Disabling/enabling a cache has no effect on contents of the cache: valid data stays valid, locked
items remain locked and accesses that hit in the cache will hit. To prevent cache hits after disabling
the cache it is necessary to invalidate it. The way to prevent hits on the fill buffer is to drain it. All
operations defined in
The Drain Write Buffer function not only drains the write buffer but also drains the fill buffer. The
Intel® XScale™ core does not check permissions on addresses supplied for cache or TLB
functions. Because only privileged software may execute these functions, full accessibility is
assumed. Cache functions will not generate any of the following:
•
translation faults
•
domain faults
•
permission faults
Since the Clean D Cache Line function reads from the data cache, it is capable of generating a
parity fault. The other operations will not generate parity faults.
The invalidate instruction cache line command does not invalidate the BTB. If software invalidates
a line from the instruction cache and modifies the same location in external memory, it needs to
invalidate the BTB also. Not invalidating the BTB in this case will cause unpredictable results.
Table 7-12. Cache Functions (Sheet 1 of 2)
Invalidate I&D cache & BTB
Invalidate I cache & BTB
Invalidate I cache line
Invalidate D cache
Invalidate D cache line
Clean D cache line
Intel® XScale™ Microarchitecture User's Manual
Access
Read / Write
Table 7-12
work regardless of whether the cache is enabled or disabled.
Function
opcode_2
0b000
0b000
0b001
0b000
0b001
0b001
Fault Virtual Address
Fault Virtual Address - Contains the MVA of the data
access that caused the memory abort
CRm
Data
0b0111
Ignored
0b0101
Ignored
0b0101
MVA
0b0110
Ignored
0b0110
MVA
0b1010
MVA
Configuration
8
7
6
5
4
3
2
Description
Instruction
MCR p15, 0, Rd, c7, c7, 0
MCR p15, 0, Rd, c7, c5, 0
MCR p15, 0, Rd, c7, c5, 1
MCR p15, 0, Rd, c7, c6, 0
MCR p15, 0, Rd, c7, c6, 1
MCR p15, 0, Rd, c7, c10, 1
1
0
7-9
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