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9.3
Instruction Register
The instruction register (IR) holds instruction codes shifted through the Test Data Input (TDI) pin.
Instruction codes in this register select the specific test operation performed and the test data
register accessed. These instructions can be either mandatory or optional as set forth in the IEEE
Std. 1149.1a-1993, user-defined, or private.
The instruction register is a 5-bit wide serial shift register. Data is loaded into the IR serially
through the TDI pin clocked by the rising edge of TCK when the TAP controller is in the Shift_IR
state.
The most significant bit of the IR is connected to TDI, and the least significant bit is connected to
TDO. TDI is shifted into IR on the rising edge of TCK, as long as TMS remains asserted.
Upon activation of the nTRST pin, the latched instruction asynchronously changes to the idcode
instruction.
9.3.1
Boundary-Scan Instruction Set
The application processor supports three mandatory public boundary scan instructions: extest,
sample/preload, bypass. It also supports three optional public instructions: idcode, clamp, highz,
four user-defined instructions: dbgrx, ldic, dcsr, dbgtx, and fourteen private instructions. The
application processor does not support the optional public instructions runbist, intest, or
usercode.
of these instructions in detail.
Table 9-2. JTAG Instruction Codes
Instruction Code
00000
2
00001
2
00010
2
00011
2
00100
2
00101
2
00110
2
00111
2
01000
2
01001
2
Intel® XScale™ Microarchitecture User's Manual
Table 9-2
summarizes these boundary-scan instruction codes.
Instruction Name
extest
sample/preload
dbgrx
private
clamp
private
not used
ldic
highz
dcsr
Instruction Code
01010
2
01011
2
01100
2
01101
2
01110
- 01111
2
2
10000
2
10001
- 11001
2
2
11010
- 11101
2
2
11110
2
11111
2
Test
Table 9-3
describes each
Instruction Name
private
private
private
private
not used
dbgtx
private
not used
idcode
bypass
9-3
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