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Memory Management
3.2.1
Version 4 vs. Version 5
ARM* MMU Version 5 Architecture introduces the support of tiny pages, which are 1 KByte in
size. The reserved field in the first-level descriptor (encoding 0b11) is used as the fine page table
base address. The exact bit fields and the format of the first and second-level descriptors are found
in
Section 2.3.2, "New Page Attributes" on page
The attributes associated with a particular region of memory are configured in the memory
management page table and control the behavior of accesses to the instruction cache, data cache,
mini-data cache, and the write buffer. These attributes are ignored when the MMU is disabled.
To allow compatibility with older system software, the new Intel® XScale™ core attributes take
advantage of encoding space in the descriptors that were formerly reserved and defaulted to zero.
3.2.2
Instruction Cache
When examining the X, C, and B bits in a descriptor, the Instruction Cache only utilizes the C bit.
If the C bit is clear, the Instruction Cache considers a code fetch from that memory to be non-
cacheable, and will not fill a cache entry. If the C bit is set, then fetches from the associated
memory region will be cached.
3.2.3
Data Cache and Write Buffer
All of the X, C & B descriptor bits affect the behavior of the Data Cache and the Write Buffer.
If the X bit for a descriptor is zero, the C and B bits operate as mandated by the ARM* architecture.
This behavior is detailed in
If the X bit for a descriptor is one, the C and B bits' meaning is extended, as detailed in
Table 3-1. Data Cache and Buffer Behavior when X = 0
C B
Cacheable?
0 0
b
0 1
c
1 0
1 1
a.
Normally, the processor will continue executing after a data access if no dependency on that access is encountered. With
this setting, the processor will stall execution until the data access completes. This guarantees to software that the data ac-
cess has taken effect by the time execution of the data access instruction completes. External data aborts from such access-
es will be imprecise (but see
b.
Different from StrongARM, which for these attributes did not coalesce in the Write Buffer
c.
Different from StrongARM, which for these attributes selected the mini data cache, see when X = 1
3-2
Table
3-1.
Bufferable?
N
N
N
Y
Y
Y
Y
Y
Section 2.3.4.4
for a method to shield code from this imprecision).
2-9.
Line
Write Policy
Allocation
Policy
-
-
-
-
Write Through
Read Allocate
Write Back
Read Allocate
Intel® XScale™ Microarchitecture User's Manual
Table
3-2.
Notes
a
Stall until complete
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