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Globally invalidating a TLB will not affect locked TLB entries. However, the invalidate-entry
operations can invalidate individual locked entries. In this case, the locked entry remains in the
TLB, but will never "hit" on an address translation. Effectively, a hole is in the TLB. This situation
can be rectified by unlocking the TLB.
3.4.2
Enabling/Disabling
The MMU is enabled by setting bit 0 in coprocessor 15, register 1 (Control Register).
When the MMU is disabled, accesses to the instruction cache default to cacheable and all accesses
to data memory are made non-cacheable.
A recommended code sequence for enabling the MMU is shown in
Example 3-1. Enabling the MMU
; This routine provides software with a predictable way of enabling the MMU.
; After the CPWAIT, the MMU is guaranteed to be enabled. Be aware
; that the MMU will be enabled sometime after MCR and before the instruction
; that executes after the CPWAIT.
; Programming Note: This code sequence requires a one-to-one virtual to
; physical address mapping on this code since
; the MMU may be enabled part way through. This would allow the instructions
; after MCR to execute properly regardless of the state of the MMU.
MRC P15,0,R0,C1,C0,0; Read CP15, register 1
ORR R0, R0, #0x1; Turn on the MMU
MCR P15,0,R0,C1,C0,0; Write to CP15, register 1
; For a description of CPWAIT, see
;
Section 2.3.3, "Additions to CP15 Functionality" on page 2-10
CPWAIT
; The MMU is guaranteed to be enabled at this point; the next instruction or
; data address will be translated.
3.4.3
Locking Entries
Individual entries can be explicitly loaded & locked into the instruction and data TLBs. See
Table 7-16, "TLB Lockdown Functions" on page 7-12
Note: If a lock operation finds the virtual address translation already resident in the TLB, the results are
unpredictable. An invalidate entry command, see
before the lock command will ensure proper operation. Software can also accomplish this by
invalidating all entries, as shown in
Locking entries into either the instruction TLB or data TLB reduces the available number of entries
(by the number that was locked down) for hardware to cache other virtual to physical address
translations.
A procedure for locking entries into the instruction TLB is shown in
Intel® XScale™ Microarchitecture User's Manual
for the exact commands.
Table 7-13, "TLB Functions" on page
Example 3-2 on page
3-6.
Memory Management
Equation
3-1.
7-11,
Example 3-2 on page
3-6.
3-5
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