Reset; Update Policy; Btb Control; Disabling/Enabling - Intel PXA255 User Manual

Branch Target Buffer
Figure 5-2. Branch History
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5.1.1

Reset

After Processor Reset, the BTB is disabled and all entries are invalidated.
5.1.2

Update Policy

A new entry is stored into the BTB when the following conditions are met:
•
the BTB is enabled
•
the branch instruction has executed
•
the branch was taken
•
the branch is not currently in the BTB
The entry is then marked valid and the history bits are set to WT. If another valid branch exists at
the same entry in the BTB, it will be evicted by the new branch.
Once a branch is stored in the BTB, the history bits are updated upon every execution of the branch
as shown in
5.2

BTB Control

5.2.1

Disabling/Enabling

The BTB is always disabled with Reset. Software enables the BTB through the Control Register
bit[11] in coprocessor 15 (see
5-2
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WN
SN
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SN: Strongly Not Taken
WN: Weakly Not Taken
Figure 5-2.
Section
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WT
7.2.2).
Intel® XScale™ Microarchitecture User's Manual
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ST
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ST: Strongly Taken
WT: Weakly Taken
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