Loading Ic During A Warm Reset For Debug - Intel PXA255 User Manual

Software Debug
An additional issue for debug is setting up the reset vector trap. This must be done before the
internal reset signal is de-asserted. As described in
Reset bits in the DCSR must be set prior to de-asserting reset in order to trap the reset vector. There
are two possibilities for setting up the reset vector trap:
•
The reset vector trap can be set up before the instruction cache is loaded by scanning in a
DCSR value that sets the Trap Reset bit in addition to the Halt Mode bit and the hold_rst
signal.
•
The reset vector trap can be set up after the instruction cache is loaded. In this case, the DCSR
should be set up to do a reset vector trap, with the Halt Mode bit and the hold_rst signal
remaining set.
In either case, when the debugger clears the hold_rst bit to de-assert internal reset, the debugger
must have already set the Halt Mode and Trap Reset bits in the DCSR.
10.13.4.2

Loading IC During a Warm Reset for Debug

Loading the instruction cache during a warm reset is a slightly different situation than during a cold
reset. For a warm reset, the main issue is whether the instruction cache gets invalidated by the
processor reset or not.
There are several possible scenarios:
•
While reset is asserted, TRST is also asserted.
In this case the instruction cache is invalidated, so the actions taken to download code are
identical to those described in
•
When reset is asserted, TRST is not asserted, but the processor is not in Halt Mode.
In this case, the instruction cache is also invalidated, so the actions are the same as described in
Section
•
When reset is asserted, TRST is not asserted, and the processor is in Halt Mode.
In this last scenario, the mini instruction cache does not get invalidated by reset, since the
processor is in Halt Mode. This scenario is described in more detail in this section.
The last scenario described above is shown in
10-36
Section 10.13.4.1
10.13.4.1, after the LDIC instruction is loaded into the JTAG IR.
Section 10.3.3, the Halt Mode and the Trap
Figure 10-12.
Intel® XScale™ Microarchitecture User's Manual