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The pitfall is when the write to memory stalls long enough that the assumption fails. In this case the
download with normal handshaking can be used (or high-speed download can still be used, but a
few extra TCKs in the Pause_DR state may be necessary to allow a little more time for the store to
complete).
The hardware support for high-speed download includes the Download bit (DCSR[29]) and the
Overflow Flag (DCSR[30]).
The download bit acts as a branch flag, signalling to the handler to continue with the download.
This removes the need for a counter in the debug handler.
The overflow flag indicates that the debugger attempted to download the next word before the
debug handler read the previous word.
More details on the Download bit, Overflow flag and high-speed download, in general, can be
found in
Section 10, "Transmit/Receive Control Register
Following is example code showing how the Download bit and Overflow flag are used in the
debug handler:
hs_write_word_loop:
hs_write_overflow:
bl
@@ read TXRXCTRL into the CCs
mrc
bcc
beq
str
b
hs_write_done:
@@ after the loop, if the overflow flag was set, return error message to host
moveq
beq
b
10.14.3
Ending a Debug Session
Prior to ending a debug session, the debugger must take the following actions:
1. Clear the DCSR (disable debug, exit Halt Mode, clear all vector traps, disable the trace buffer)
2. turn off all breakpoints;
3. invalidate the mini instruction cache;
4. invalidate the main instruction cache;
5. invalidate the BTB;
These actions ensure that the application program executes correctly after the debugger has been
disconnected.
Intel® XScale™ Microarchitecture User's Manual
read_RX
p14, 0, r15, c14, c0, 0
hs_write_done
@ if D bit clear, download complete, exit loop.
hs_write_overflow
@ if overflow detected, loop until host clears D bit
r0, [r6], #4
@ store only if there is no overflow.
hs_write_word_loop
r0, #OVERFLOW_RESPONSE
send_response
write_common_exit
(TXRXCTRL)".
@ read data word from host
@ get next data word
Software Debug
10-45
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