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Introduction
1.1
About This Document
This document describes the Intel® XScale™ core as implemented in the PXA255 processor.
Intel Corporation assumes no responsibility for any errors which may appear in this document nor
does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice. In
particular, descriptions of features, timings, and pin-outs does not imply a commitment to
implement them.
1.1.1
How to Read This Document
It is necessary to be familiar with the ARM* Version 5TE Architecture in order to understand some
aspects of this document.
Each chapter in this document focuses on a specific architectural feature of the Intel® XScale™
core.
•
Chapter 2, "Programming Model"
•
Chapter 3, "Memory Management"
•
Chapter 4, "Instruction Cache"
•
Chapter 5, "Branch Target Buffer"
•
Chapter 6, "Data Cache"
•
Chapter 7, "Configuration"
•
Chapter 8, "Performance Monitoring"
•
Chapter 10, "Software Debug"
•
Chapter 11, "Performance Considerations"
•
Appendix A, "Optimization Guide"
Note: Most of the "buzz words" and acronyms found throughout this document are captured in
Section 1.3.2, "Terminology and Acronyms" on page
1.1.2
Other Relevant Documents
•
ARM* Architecture Reference Manual Document Number: ARM DDI 0100E
This document describes the ARM* Architecture and is publicly available.
See http://www.arm.com/ARMARM for details. Sold as:
ARM* Architecture Reference Manual
Second Edition, edited by David Seal: Addison-Wesley: ISBN 0-201-73719-1
•
Intel® PXA255 Processor Developer's Manual, Intel Order # 278693
Intel® XScale™ Microarchitecture User's Manual
covers instruction scheduling techniques.
1-6, located at the end of this chapter.
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