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Instruction Cache
Example 4-1. Recovering from an Instruction Cache Parity Error
; Prefetch abort handler
MCR P15,0,R0,C7,C5,0
CPWAIT
SUBS PC,R14,#4
If a parity error occurs on an instruction that is locked in the cache, the software exception handler
needs to unlock the instruction cache, invalidate the cache and then re-lock the code in before it
returns to the faulting instruction.
4.2.6
Instruction Fetch Latency
The instruction fetch latency is dependent on the core to memory frequency ratio, system bus
bandwidth, system memory, etc. The outstanding external memory bus activity on the PXA255
processor will have the highest impact on instruction fetch latency.
4.2.7
Instruction Cache Coherency
The instruction cache does not detect modification to program memory by loads, stores or actions
of other bus masters. Several situations may require program memory modification, such as
uploading code from disk.
The application program is responsible for synchronizing code modification and invalidating the
cache. In general, software must ensure that modified code space is not accessed until both
memory modification and invalidation of the instruction cache are completed.
To achieve cache coherence, instruction cache contents can be invalidated after code modification
in external memory is complete. Refer to
page 4-5
If the instruction cache is not enabled, or code is being written to a non-cacheable region, software
must still invalidate the instruction cache before using the newly-written code. This precaution
ensures that state associated with the new code is not buffered elsewhere in the processor, such as
the fetch buffers or the BTB.
When writing code into memory the writes involve the data cache not the instruction cache. Care
must be taken to force writes completely out of the processor data path into external memory
before attempting to execute the code. If writing into a non-cacheable region, flushing the write
buffers is sufficient precaution (see
cacheable region, then the data cache should be submitted to a Clean/Invalidate operation (see
Section
6.3.3.1) to ensure coherency. Any data cache cleaning must be done before the previously
mentioned instruction cache invalidation. This typically applies to code that is created, being
modified, or simply written into memory, prior to code execution. Typical examples would be
copying ROM code to DRAM, or dynamic libraries.
4-4
; Invalidate the instruction cache and branch target
; buffer
; wait for effect (see
; description of CPWAIT)
; Returns to the instruction that generated the
; parity error
for the proper procedure for invalidating the instruction cache.
Section 2.3.3
Section 4.3.3, "Invalidating the Instruction Cache" on
Section 7.2.7
for a description of this operation). If writing to a
Intel® XScale™ Microarchitecture User's Manual
for a
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