High Level View Of Trace Buffer - Intel PXA255 User Manual

Software Debug
Figure 10-6. High Level View of Trace Buffer
The trace buffer must be initialized prior to its initial usage, then again prior to each subsequent
usage. Initialization is done be reading the entire trace buffer. The process of reading the trace
buffer also clears it out (all entries are set to 0b00000000), so when the trace buffer has been used
to capture a trace, the process of reading the captured trace data also re-initializes the trace buffer
for its next usage.
The trace buffer can be used to capture a trace up to a processor reset. A processor reset disables
the trace buffer, but does not affect the contents. The trace buffer does not capture reset events or
debug exceptions.
Since the trace buffer is cleared out before it is used, all entries are initially 0b00000000. In fill-
once mode, these 0's can be used to identify the first valid entry in the trace buffer. In wrap around
mode, in addition to identifying the first valid entry, these 0 entries can be used to determine
whether a wrap around occurred.
As the trace buffer is read, the oldest entries are read first. Reading a series of 5 (or more)
consecutive "0b00000000" entries in the oldest entries indicates that the trace buffer has not
wrapped around and the first valid entry will be the first non-zero entry read out.
Reading 4 or less consecutive "0b00000000" entries requires a bit more intelligence in the host
software. The host software must determine whether these 0's are part of the address of an indirect
branch message, or whether they are part of the "0b00000000" that the trace buffer was initialized
with. If the first non-zero message byte is an indirect branch message, then these 0's are part of the
address since the address is always read before the indirect branch message (see
"Address
indicate that the trace buffer has not wrapped around and that first non-zero entry is the start of the
trace.
10-26
first byte read
(oldest entry)
CHKPT1
CHKPT0
last byte read
(most recent entry)
Bytes"). If the first non-zero entry is any other type of message byte, then these 0's
target[7:0]
1001 CCCC (indirect)
1000 CCCC (direct)
1100 CCCC (direct)
. . .
1111 1111 (roll-over)
target[31:24]
target[23:16]
target[15:8]
target[7:0]
1101 CCCC (indirect)
1000 CCCC (direct)
1111 1111 (roll-over)
1000 CCCC (direct)
Intel® XScale™ Microarchitecture User's Manual
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