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Software Debug
When a debug exception occurs, the processor's actions depend on whether the debug unit is
configured for Halt mode or Monitor mode.
Table 10-4
Table 10-4. Event Priority
Reset
Vector Trap
Data Abort (precise)
Data Breakpoint
Data Abort (imprecise)
External debug break, Trace-buffer full
FIQ
IRQ
Instruction Breakpoint
Prefetch Abort
Undefined, SWI, BKPT
a.
See
"Vector Trap Bits (TF,TI,TD,TA,TS,TU,TR)" on page 10-4
10.4.1
Halt Mode
The debugger turns on Halt mode through the JTAG interface by scanning in a value that sets the
bit in DCSR. The debugger turns off Halt mode through JTAG, either by scanning in a new DCSR
value or by a TRST. Processor reset does not effect the value of the Halt mode bit.
When halt mode is active, the processor uses the reset vector as the debug vector. The debug
handler and exception vectors can be downloaded directly into the instruction cache, to intercept
the default vectors and reset handler, or they can be resident in external memory. Downloading into
the instruction cache allows a system with memory problems, or no external memory, to be
debugged. Refer top
for details about downloading code into the instruction cache.
During Halt mode, software running on the Intel® XScale™ core cannot access DCSR, or any of
hardware breakpoint registers, unless the processor is in Special Debug State (SDS), described
below.
When a debug exception occurs during Halt mode, the processor takes the following actions:
•
disables the trace buffer
•
sets DCSR.moe encoding
•
processor enters a Special Debug State (SDS)
•
for data breakpoints, trace buffer full break, and external debug break:
R14_dbg = PC of the next instruction to execute + 4
for instruction breakpoints and software breakpoints and vector traps:
R14_dbg = PC of the aborted instruction + 4
•
SPSR_dbg = CPSR
10-6
shows the priority of debug exceptions relative to other processor exceptions.
Event
a
Section 10.13, "Downloading Code into the Instruction Cache" on page 10-30
Priority
for vector trap options
Intel® XScale™ Microarchitecture User's Manual
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