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Software Debug
remain in the JTAG IR for a minimum of 15 TCKs. This ensures the last packet is correctly sent to
the instruction cache.
10.13.3
LDIC Cache Functions
The Intel® XScale™ core supports four cache functions that can be executed through JTAG. Two
functions allow an external host to download code into the main instruction cache or the mini
instruction cache through JTAG. Two additional functions are supported to allow lines to be
invalidated in the instruction cache. The following table shows the cache functions supported
through JTAG.
Table 10-20. LDIC Cache Functions
Invalidate IC Line
Invalidate Mini IC
Invalidate IC line invalidates the line in the instruction cache containing specified virtual address.
If the line is not in the cache, the operation has no effect. It does not take any data arguments.
Invalidate Mini IC will invalidate the entire mini instruction cache. It does not effect the main
instruction cache. It does not require a virtual address or any data arguments.
Load Main IC and Load Mini IC write one line of data (8 ARM* instructions) into the specified
instruction cache at the specified virtual address.
The LDIC Invalidate Mini I-Cache function does not invalidate the BTB (like the CP15 Invalidate
IC function) so software must do this manually where appropriate.
10-32
Function
Load Main IC
Load Mini IC
RESERVED
0b100-0b111
Encoding
Address
0b000
VA of line to invalidate
0b001
0b010
VA of line to load
0b011
VA of line to load
Intel® XScale™ Microarchitecture User's Manual
Arguments
# Data Words
0
-
0
8
8
-
-
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