Power-On Reset Timing - Intel PXA255 Datasheet

Note: If hardware reset is entered during sleep mode, follow the proper power-supply stabilization times
indicated in
Figure 3. Power-On Reset Timing
VCCQ, PWR_EN
NOTES:
1. nBATT_FAULT and nVDD_FAULT must be high before nRESET_OUT is deasserted or the
processor enters sleep mode.
2. The inclusion of PWR_EN is for informational purposes only to show its relationship to VCCQ. The
use of PWR_EN to bring up VCCN or VCC at power-on reset is optional depending on the system's
power management requirements. VCCN and VCC are not dependant on the PWR_EN signal being
asserted.
Table 15. Power-On Timing Specifications
Symbol
tR_VCCQ
tR_VCCN
tR_VCC
tD_VCCN
tD_VCC
tD_NTRST
tD_JTAG
tD_NRESET
tD_OUT
tD_NCS0
Intel® PXA255 Processor Electrical, Mechanical, and Thermal Specification
Figure 3 and nRESET timing requirements indicated in
VCCN
VCC
nTRST
JTAG PINS
nRESET
nRESET_OUT
Description
VCCQ rise / stabilization time
VCCN rise / stabilization time
VCC, PLL_VCC rise / stabilization time
Delay between VCCQ applied and
VCCN applied
Delay from VCCN applied and VCC,
PLL_VCC applied
Delay between VCC, PLL_VCC stable
and nTRST de-asserted
Delay between nTRST de-asserted and
JTAG pins active, with nRESET
asserted
Delay between VCC, PLL_VCC stable
and nRESET de-asserted
Delay between nRESET de-asserted
and nRESET_OUT de--asserted
Delay between nRESET_OUT
deasserted and nCS0 asserted
t
R_VCCQ
t
R_VCCN
t
D_VCCN
t
R_VCC
t
D_VCC
t
D_NTRST
Min
0.01
0.01
0.01
0
-10
10
0.03
10
18.1
400
Electrical Specifications
Table 15.
t
D_JTAG
t
D_NRESET
t
D_OUT
Typical Max Units
— 100
— 100
— 10
— —
— —
— —
— —
— —
— 18.2
— 420
ms
ms
ms
ms
ms
ms
ms
ms
ms
ns
31