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Performance Monitoring
This chapter describes the performance monitoring facility of the Intel® XScale™ core. The events
that are monitored provide performance information for compiler writers, system application
developers and software programmers.
8.1
Overview
The Intel® XScale™ core hardware provides two 32-bit performance counters that allow two
unique events to be monitored simultaneously. In addition, the Intel® XScale™ core implements a
32-bit clock counter that can be used in conjunction with the performance counters; its sole
purpose is to count the number of core clock cycles which is useful in measuring total execution
time.
The Intel® XScale™ core can monitor either occurrence events or duration events. When counting
occurrence events, a counter is incremented each time a specified event takes place and when
measuring duration, a counter counts the number of processor clocks that occur while a specified
condition is true. If any of the 3 counters overflow, an IRQ or FIQ will be generated if it's enabled.
Each counter has its own interrupt enable. The counters continue to monitor events even after an
overflow occurs, until disabled by software.
Each of these counters can be programmed to monitor any one of various events.
To further augment performance monitoring, the Intel® XScale™ core clock counter can be used
to measure the executing time of an application. This information combined with a duration event
can feedback a percentage of time the event occurred with respect to overall execution time.
Each of the three counters and the performance monitoring control register are accessible through
Coprocessor 14 (CP14), registers 0-3. Refer to
Monitoring" on page 7-16
and STC coprocessor instructions. Access is allowed in privileged mode only.
8.2
Clock Counter (CCNT; CP14 - Register 1)
The format of CCNT is shown in
Monitor Control Register (PMNC) or can be set to a predetermined value by directly writing to it.
It counts core clock cycles. When CCNT reaches its maximum value 0xFFFF_FFFF, the next clock
cycle will cause it to roll over to zero and set the overflow flag (bit 10) in PMNC. An IRQ or FIQ
will be reported if it is enabled via bit 6 in the PMNC register.
The CCNT register continues running in DEBUG mode, yet will become unpredictable if the
Power Mode register, see
page 7-16
Intel® XScale™ Microarchitecture User's Manual
for more details on accessing these registers with MRC, MCR, LDC,
Table
Section 7.3.2, "Registers 6-7: Clock and Power Management" on
is written as non-ACTIVE.
Section 7.3.1, "Registers 0-3: Performance
8-1. The clock counter is reset to '0' by Performance
8
8-1
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