System Bus Reset And Configuration Timings For Warm Reset - Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Manual

Warm Reset Sequence:
• PWRGOOD remains high throughout the entire sequence, as power is already
available and stable to the processor.
• The configuration pins (A[21:17]#) must be asserted the entire time RESET# is
asserted.
• The duration from the assertion of RESET# to the deassertion of RESET# must be 1
millisecond minimum.
• After RESET# is deasserted, the configuration pins must remain valid for two
BCLKs (minimum) to three BCLKs (maximum).
• BCLK is shown as a time reference to the BCLK period. It is not a requirement that
this is BCLKn or BCLKp signal.
• Configuration signals other than A[21:17]# must be asserted four BCLKs prior to
the deasserted edge of RESET# and must remain valid for two BCLKs (minimum) to
three BCLKs (maximum) after the deasserted edge of RESET#.
Figure 2-6
PWRGOOD for warm reset.
Figure 2-6.

System Bus Reset and Configuration Timings for Warm Reset

BCLK
PWRGOOD
RESET#
Bus Ratio
(A[21:17]#)
Additional
Configuration
Signals
32
outlines the timing relationship between the configuration pins, RESET# and
T
C
T = 1.15 ns minimum; (set up time to BCLK for deassertion edge of RESET#)
A
T = 1 ms minimum for warm reset
B
T = Bus ratio signals must be asserted no later than RESET#
C
T = 2 BCLKs minimum, 3 BCLKs maximum
D
T = 4 BCLKs minimum
E
T = 2 BCLKs minimum, 3 BCLKs maximum
F
Dual-Core Intel
t t t t
-4 -3 -2 -1
T
B
T
E
® ®
Itanium Processor 9000 and 9100 Series Datasheet
Electrical Specifications
t t t t
0 1 2 3
T
A
T
D
T
F
000777b