Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3039

Status Register
The register indicates if there have been any errors, active interrupts and global lock status.
SPU_STAT
VIRQ (R/W1C)
Violation Interrupt Request
LWERR (R/W1C)
Lock Write Error
Figure 43-10: SPU_STAT Register Diagram
Table 43-9: SPU_STAT Register Fields
Bit No.
(Access)
31 LWERR
(R/W1C)
30 ADDRERR
(R/W1C)
12 VIRQ
(R/W1C)
0 GLCK
(R/NW)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13 12 11 10
0 0 0 0 0 0
31 30 29 28 27 26
0 0 0 0 0 0
Bit Name
Lock Write Error.
The SPU_STAT.LWERR indicates whether there has been an attempted write to a
register in the SPU with its lock bit (SPU_CTL.WPLCK or SCRLCK) set while
SPU_CTL.GLCK was asserted. This bit is W1C.
Address Error.
The SPU_STAT.ADDRERR indicates whether there has been an attempted write to a
read-only register or an access an invalid address in the SPU MMR address range. This
bit is W1C.
Violation Interrupt Request.
The SPU_STAT.VIRQ bit indicates that a security and/or protection violation has
been detected and interrupt asserted. This is a W1C bit.
Global Lock Status.
The SPU_STAT.GLCK indicates whether the global lock is enabled or disabled.
9 8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
25 24 23 22 21 20 19 18
0 0 0 0 0 0 0 0
Description/Enumeration
0 Inactive
1 Active
0 Inactive
1 Active
0 Inactive
1 Active
0 Disabled (global_lock=0)
1 Enabled (global_lock=1)
ADSP-SC58x SPU Register Descriptions
1 0
0 0
GLCK (R)
Global Lock Status
17 16
0 0
ADDRERR (R/W1C)
Address Error
43–15