Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3078

PKTE Programming Model
Example Configuration:
PKTE_RING_CFG.RINGSZ=256,
PKTE_RING_THRESH.RDRTHRSH=32, timeout=1ms
PKTE_INT_EN.RDRTHRSH=1
1. The Packet Engine writes the Result Descriptor, timeout counter starts.
2. The Packet Engine writes 32 more Result Descriptors, fill level
3. The fill level exceeds threshold within 1ms, the RDR threshold IRQ is activated.
4. The host handles the interrupt, reads 8 Result Descriptors at once, then writes the
ter with 8. The write to the
under the threshold but there are still 25 descriptors left.
5. The Packet Engine writes 8 more Result Descriptors, fill level increases to 33.
6. The fill level exceeds threshold within 1 ms, the RDR threshold IRQ is activated.
7. The host handles the interrupt, reads 8 Result Descriptors at once, then writes the
ter with 8. The write to the
under the threshold but there are still 25 descriptors left.
8. After 1 ms, the timeout counter interrupt is activated.
9. The host handles the interrupt, reads 8 Result Descriptors at once, then writes the
ter with 8. This is repeated until there are less than 8 full entries in the RDR. The fill level is now under the
threshold and the RDR threshold IRQ interrupt is inactive. Each write to the
restarts the timeout counter.
PKTE Programming Model
The host processor must always follow a pre-defined sequence of five phases required by the packet engine on a per
packet basis when using direct host mode. The following sections describe the five phases.
Phase 1. Write the Command Descriptor
1. Write the first command descriptor word with status and control information to the
ter.
2. Optionally, write the user ID to the
3. Write the last descriptor word to the
4. Write the value 0x1 to the
command descriptor. If the command descriptor is invalid, an error is generated. (See the
section in the Register Descriptions). If the command descriptor is valid, the packet engine waits for an
PKTE_SA_RDY register write.
44–30
/*(IRQ enabled)*/
PKTE_RDSC_DECR
PKTE_RDSC_DECR
PKTE_USERID
PKTE_LEN register.
PKTE_CDSC_CNT register. This opertion triggers the packet engine to validate the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
(PKTE_RDSC_CNT
register restarts the timeout counter. The fill level is now
register restarts the timeout counter. The fill level is now
register.
register) increases to 33.
PKTE_RDSC_DECR
PKTE_RDSC_DECR
PKTE_RDSC_DECR
PKTE_RDSC_DECR register
PKTE_CTL_STAT
PKTE_CTL_STAT
regis-
regis-
regis-
regis-