Analog Devices ADSP-SC58 Series Hardware Reference Manual page 3019

ADSP-SC58x HADC Register Descriptions
Interrupt Mask Register
The register masks (disables) or unmasks (enables) the interrupts as programmed. The reset value of
HADC_IMSK
the HADC_IMSK register is 0x08, masking these interrupts after reset.
CHAN (R/W)
Channel Mask
RDY (R/W)
Mask interrupt when ADC ready to
convert
Figure 41-8: HADC_IMSK Register Diagram
Table 41-10: HADC_IMSK Register Fields
Bit No.
(Access)
17 RDY
(R/W)
16 SEQ
(R/W)
15:0 CHAN
(R/W)
41–14
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
Bit Name
Mask interrupt when ADC ready to convert.
The HADC_IMSK.RDY bit masks the interrupt generated when ADC is ready to con-
vert.
Mask interrupt at end of sequence completion.
The HADC_IMSK.SEQ bit masks the interrupt which is generated at the end of se-
quence completion.
Channel Mask.
The HADC_IMSK.CHAN bit field provides the interrupt mask bit for each channel. N
ranges from 0-15. The MSB corresponds to channel 15, the second MSB to channel
14 and so on. If the interrupt mask for a particular channel is high, no interrupt is
generated when that channel finishes the end of data conversion.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
0 Interrupt is unmasked
1 Interrupt is masked
SEQ (R/W)
Mask interrupt at end of sequence
completion