EMAC Control Module Registers
3.5
EMAC Control Module Receive Threshold Interrupt Enable Register
(CMRXTHRESHINTEN)
The receive threshold interrupt enable register (CMRXTHRESHINTEN) is shown in
described in
Table
Figure 17. EMAC Control Module Receive Threshold Interrupt Enable Register
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 14. EMAC Control Module Receive Threshold Interrupt Enable Register
Bit
Field
31-8
Reserved
7-0
RXTHRESHEN[n]
3.6
EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
The receive interrupt enable register (CMRXINTEN) is shown in
Figure 18. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
31
15
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 15. EMAC Control Module Receive Interrupt Enable Register (CMRXINTEN)
Bit
Field
31-8
Reserved
7-0
RXPULSEEN[n]
64
Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO)
14.
(CMRXTHRESHINTEN)
R-0
(CMRXTHRESHINTEN) Field Descriptions
Value
Description
0
Reserved
Receive threshold interrupt (RXTHRESHPENDn) enable. Each bit controls the corresponding
channel n receive threshold interrupt.
Bit n = 0, channel n receive threshold interrupt (RXTHRESHPENDn) is disabled.
Bit n = 1, channel n receive threshold interrupt (RXTHRESHPENDn) is enabled.
R-0
Field Descriptions
Value
Description
0
Reserved
Receive interrupt (RXPENDn) enable. Each bit controls the corresponding channel n receive
interrupt.
Bit n = 0, channel n receive interrupt (RXPENDn) is disabled.
Bit n = 1, channel n receive interrupt (RXPENDn) is enabled.
Reserved
R-0
8
7
Figure 18
Reserved
R-0
8
7
www.ti.com
Figure 17
and
RXTHRESHEN
R/W-0
and described in
Table
RXPULSEEN
R/W-0
SPRUEQ6 – December 2007
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16
0
15.
16
0