Operation In Power Save Mode; Bus Hold Timing - NEC V850E/IA1 mPD703116 User Manual

4.8.3 Operation in power save mode

In the software STOP or IDLE mode, the internal system clock is stopped. Consequently, the bus hold state is not
accepted and set since the HLDRQ pin cannot be accepted even if it becomes active.
In the HALT mode, the HLDAK pin immediately becomes active when the HLDRQ pin becomes active, and the bus
hold state is set. When the HLDRQ pin becomes inactive after that, the HLDAK pin also becomes inactive. As a
result, the bus hold state is cleared and the HALT mode is set again.

4.8.4 Bus hold timing

CLKOUT (output)
HLDRQ (input)
HLDAK (output)
A16 to A23 (output)
AD0 to AD15 (I/O)
ASTB (output)
RD (output)
LWR, UWR (output)
CSn (output)
WAIT (input)
Remarks 1. The circles indicate the sampling timing.
2. The broken lines indicate the high-impedance state.
3. n = 0 to 7
CHAPTER 4 BUS CONTROL FUNCTION
T2 T3
Address
Address Data
User's Manual U14492EJ3V0UD
TH TH TH TH TI T1
Undefined Address
Undefined Address
129