Sram, External Rom, External I/O Access; Figure 5-2: Sram, External Rom, External I/O Access Timing (1/6) - NEC V850E/CA1 ATOMIC Preliminary User's Manual

5.1.3 SRAM, external ROM, external I/O access

Figure 5-2: SRAM, External ROM, External I/O Access Timing (1/6)

CLKOUT (output)
A0 to A23 (output)
CSn (output)
RD (output)
UWR (output)
LWR (output)
D0 to D15 (I/O)
WAIT (input)
Remarks: 1. The circles
2. The broken line indicates the high-impedance state.
3. CSn = CS2 to CS4
Chapter 5 Memory Access Control Function
T1
Address
indicate the sampling timing.
Preliminary User's Manual U14913EE1V0UM00
(a) During read
T2 T1 TW
Address
Data
T2
Data
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