Bus Hold Timing - NEC V850E/MS1 UPD703100 User Manual

32-/16-bit single-chip microcontrollers

Table of Contents

4.8.4 Bus hold timing

Note If HLDRQ signal is inactive (high level) at this sampling timing, bus hold state is not entered.

Remarks 1. The circle indicates the sampling timing.

2. The broken lines indicate high impedance.

3. n = 0 to 7

4. Timing from DRAM access to bus hold state.

CHAPTER 4 BUS CONTROL FUNCTION

Column address

User's Manual U12688EJ4V0UM00