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6.6.2 External bus cycles during DMA transfer (two-cycle transfer)
The external bus cycles during DMA transfer (two-cycle transfer) are shown below.
Table 6-2. External Bus Cycles During DMA Transfer (Two-Cycle Transfer)
Transfer Target
On-chip peripheral I/O, internal RAM
External memory, external I/O
6.7 DMA Channel Priorities
The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
In the block transfer mode, the channel used for transfer is never switched.
In the single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is released, the
higher priority DMA transfer request is acknowledged.
Caution Be sure not to activate multiple DMA channels using the same start factor. If multiple channels
are activated in this way, a lower priority DMA channel may be acknowledged prior to a higher
priority DMA channel.
6.8 Next Address Setting Function
The DMA source address registers (DSAnH, DSAnL), DMA destination address registers (DDAnH, DDAnL), and
DMA transfer count register (DBCn) are 2-stage FIFO buffer registers configured with a master register and slave
register (n = 0 to 3).
When the terminal count is issued, these registers are automatically rewritten with the value that was set
immediately before.
If new DMA transfer setting is made to these registers during DMA transfer, therefore, the values of the registers
are automatically updated to the new value after completion of transfer
Note Before making another DMA transfer setting, confirm that DMA transfer has started. If new settings are
made before DMA transfer starts, the set values are overwritten to both the master and slave registers,
preventing the DMA transfer based on the set value immediately before from being correctly performed.
CHAPTER 6 DMA FUNCTIONS (DMA CONTROLLER)
None
Yes
SRAM, external ROM, external I/O access cycle
User's Manual U15195EJ5V0UD
External Bus Cycle
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Note
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