Transfer Object; Transfer Type And Transfer Object; Dma Channel Priorities; Table 6-1: Relationship Between Transfer Type And Transfer Object - NEC V850E/CA1 ATOMIC Preliminary User's Manual

6.7 Transfer Object

6.7.1 Transfer type and transfer object

Table 6-1 lists the relationships between transfer type and transfer object (√: transfer enabled, ×: trans-
fer disabled).

Table 6-1: Relationship Between Transfer Type and Transfer Object

On-chip peripheral I/O
External I/O
Internal RAM
External memory
Internal ROM
Cautions: 1. The operation is not guaranteed for combinations of transfer destination and
source marked with "×" in Table 6-1.
2. Addresses between 3FFF000H and 3FFFFFFH cannot be specified for the source
and destination address of DMA transfer. Be sure to specify an address between
FFFF000H and FFFFFFFH.

6.8 DMA Channel Priorities

The DMA channel priorities are fixed as follows.
DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3
These priorities are valid in the TI state only. In the block transfer mode, the channel used for transfer is
never switched.
In the single-step transfer mode, if a higher priority DMA transfer request is issued while the bus is
released (in the TI state), the higher priority DMA transfer request is acknowledged.
Chapter 6 DMA Functions (DMA Controller)
Internal
ROM
×
×
×
×
×
Preliminary User's Manual U14913EE1V0UM00
Destination
Two-Cycle Transfer
On-Chip External
Peripheral I/O
I/O
√
×
× ×
√
×
× ×
× ×
Internal External
RAM Memory
√
×
× ×
× ×
× ×
× ×
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