Simplified Timing Diagram Of Mb88121B (Multiplexed Access) - Fujitsu MB88121 Application Note

3.1.2 Simplified timing diagram of MB88121B (multiplexed access)

Following timing needs to be setup in MB91460 series when using 16-bit multiplexed
access.
Operation sequence:
1. The address is latched by the rising edge of AS pin (signal
2. The RD pin (signal
AD[10:0] is invalid.
3. After that the RDY pin becomes low level at the next rising edge of the clock signal
BCLK (pin BCLK), which causes the MCU to wait.
4. After several wait cycles the RDY pin becomes high level at the rising edge of the
BCLK pin and the valid data is output from the pins D[15:11] and AD[10:0].
5. When the RD pin becomes high level again, the read access is finished. Pins
D[15:11] and AD[10:0] become Hi-Z.
Note:
Details about RDY wait cycle and byte ordering are located in the
MB88121 data sheet.
© Fujitsu Microelectronics Europe GmbH
Interfacing MB91460 TO MB88121
Chapter 3 Software
Figure 3-3 MB88121 read operation (multiplexed mode)
RD
) becomes low level, the output data on pins D[15:11] and
- 17 -
AS
).
MCU-AN-300016-E-V10