Emi Considerations; Power Distribution And Decoupling; Decoupling; Decoupling Recommendations - Intel 80331 Design Manual

I/o processor
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Intel® 80331 I/O Processor Design Guide
Routing Guidelines
4.3

EMI Considerations

It is highly recommended that good EMI design practices be followed when designing with the
80331.
To minimize EMI on your PCB a useful technique is to not extend the power planes to the
edge of the board.
Another technique is to surround the perimeter of your PCB layers with a GND trace. This
helps to shield the PCB with grounds minimizing radiation.
The below link can provide some useful general EMI guidelines considerations:
http://developer.intel.com/design/auto/mcs96/applnots/272673.htm
4.4

Power Distribution and Decoupling

Have ample decoupling to ground, for the power planes, to minimize the effects of the switching
currents. Three types of decoupling are: the bulk, the high-frequency ceramic, and the inter-plane
capacitors.
Bulk capacitance consist of electrolytic or tantalum capacitors. These capacitors supply large
reservoirs of charge, but they are useful only at lower frequencies due to lead inductance
effects. The bulk capacitors can be located anywhere on the board.
For fast switching currents, high-frequency low-inductance capacitors are most effective.
Place these capacitors as close to the device being decoupled as possible. This minimizes the
parasitic resistance and inductance associated with board traces and vias.
Use an inter-plane capacitor between power and ground planes to reduce the effective plane
impedance at high frequencies. The general guideline for placing capacitors is to place
high-frequency ceramic capacitors as close as possible to the module.
4.4.1

Decoupling

Inadequate high-frequency decoupling results in intermittent and unreliable behavior.
A general guideline recommends that you use the largest easily available capacitor in the lowest
inductance package. The high speed decoupling capacitor should be placed as close to the pin as
possible with short, wide trace.
Table 4
provides the details on the recommended decoupling capacitors for each of the voltage
planes.
Table 4.

Decoupling Recommendations

Voltage Plane
PCI/PCI-X
PCI/PCI-X
PCI/PCI-X
DDR/DDRII
34
Voltage
Pins
3.3V
VCC33
3.3V
VCC33
3.3V
VCC33
2.5/1.8V
VCC25/18
Package
C (µF)
1210
22
0603
0.1
7343
150
0603
0.1
Number of
Caps
3
12
1
14

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