Pci Design Review Checklist; Pci Routing Examples: Ixp2800 Network Processor; Ixdp2800 Pci Bus Topology Block Diagram - Intel IXP28XX Manual

6.3
Figure 71.
6.4
Hardware Design Guide
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PCI Design Review Checklist

Use the following list of requirements and recommendations for your PCI design:
•
PCI ZQ line termination:
— ZQ1 tied to V through a 31.6-Ω resistor
SS
— ZQ2 tied to V through a 28-Ω resistor
CC33
•
PCI_M66EN must be terminated accordingly.
•
PCI_IDSEL must be terminated to GND if it is a central function.
•
Unused AD/Control signals must be terminated per PCI specification.
•
For a 64-bit operation, PCI_REQ# must be sampled at assertion on the rising edge of
PCI_RST and can also be enabled via the PCI_IXP_PARAM register.
•
Loading guidelines:
— 66 MHz – four loads
— 33 MHz – eight loads
Figure 71 illustrates PCI bus topology for the IXDP2800 Advanced Development Platform.

IXDP2800 PCI Bus Topology Block Diagram

Host
Domain
®
34 bits or Intel
64 bits
21555
Non-
Transparent
Bridge

PCI Routing Examples: IXP2800 Network Processor

Figure 72 illustrates 64-bit PCI bus routing between processors and
bus routing from the IXP28XX network processor to a bridge.
® ®
Intel Intel
IXP2800 IXP2800
Network Network
Processor Processor
Ingress Egress
NPU Domain
64 bits only
Secondary PCI Primary PCI
side of the side of the
Intel 21555 Intel 21154
NTB NTB
IXP28XX Network Processor
82559 NC
®
Intel
82559 NC
21154
Transparent
PMC
Bridge
Fabric
Utility Domain
32 bits only
Figure 73 illustrates 64-bit PCI
PCI
B3406-01
121