Trace Routing; Layout Rules For Agtl Signals; Ground Reference; Reference Plane Splits - Intel Pentium III Processor 512K Design Manual

Intel recommends running simulations at the device pads for signal quality and at the device pins
for timing analysis. However, simulation results at the device pins may be used later to correlate
simulation performance against actual system measurements.
The Low Voltage Intel
from http://www.intel.com/design/pentiumiii/devtools.
3.5

Trace Routing

The following guidelines should be followed when routing the AGTL host bus signal traces:
Traces should have an impedance of 55 Ω ± 10%
•
•
The nominal trace width should be 4.5 mils.
•
The L0 and L1 lengths in Table 7 should be matched to within 0.25 inches (per net, not
between nets).
•
Minimize the number of vias and layer transitions.
•
Minimum 10 mils spacing
3.6

Layout Rules for AGTL Signals

3.6.1

Ground Reference

It is strongly recommended that AGTL signals be routed on the signal layer next to the ground
layer (referenced to ground). It is important to provide effective signal return path with low
inductance. The best signal routing is directly adjacent to a solid GND plane with no splits or cuts.
Eliminate parallel traces between layers not separated by a power or ground plane.
3.6.2

Reference Plane Splits

Splits in reference planes disrupt signal return paths and increase overshoot/undershoot due to
significantly increased inductance. For optimal signal integrity, high-speed signals should not be
routed over power plane splits.
3.6.3

CPU Breakout

Intel strongly recommends that AGTL signals do not traverse multiple signal layers. Intel
recommends breaking out all signals from the CPU on the same layer. If routing is tight, breakout
from the CPU on the opposite routing layer over a ground reference, and cross over to the main
signal layer near the CPU.
Note: Following the above layout rules is critical for AGTL signal integrity.
3.6.4

Minimizing Crosstalk

Adhering to the following general rules will minimize the impact of crosstalk in the high speed
AGTL bus design:
•
Maximize the space between traces. Maintain a minimum of 10 mils (assuming a 4.5 mil trace)
between trace edges wherever possible. It may be necessary to use tighter spacing when
Design Guide
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LV Intel Pentium III Processor 512K Dual Processor Platform
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Pentium Processor 512K I/O Signal Integrity Models are available
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