Table of Contents
Advertisement
R
6.3.8.
Feedback – RCVENOUT#, RCVENIN#
The Intel 855GM/GME chipset GMCH provides a feedback signal called "receive enable" (RCVEN#),
which is used to measure timing for the read data.
The RCVENOUT# signal is shunted directly to RCVENIN# inside the package in order to reduce
timing variance. With this change it is no longer necessary to provide an external connection.
However, it is recommended that both signals be transitioned to the bottom side with vias located
adjacent to the package ball in order to facilitate probing.
6.4.
Routing Updates for "High-Density" Memory Device
Support
The 855GM/GME chipset architecture supports 2GB memory. This memory capacity can be achieved
using "high-density" memory devices of various package types. Intel has done only limited simulation
and bench testing on these high-density SO-DIMM memory modules and has not seen any functional or
analog inspection failures using existing layout guidelines. However, Intel has not done complete
simulation nor validation with all the available package configurations. Customers are strongly
encouraged to perform complete validation on their platforms based on the particular high-density
memory package of their choice.
6.5.
ECC Disable Guidelines
The GMCH can be configured to operate in an ECC data integrity mode that allows multiple bit error
detection and single bit error correction. This option to support ECC DDR memory modules is
dependent on design objectives. By default, ECC functionality is disabled on the platform.
6.5.1.
GMCH ECC Functionality Disable
If non-ECC memory modules are to be the only supported memory type on the platform, then the 8
DDR check bits signals, associated strobe, data mask bit, and differential clock pairs associated with the
ECC device for each SO-DIMM can be left as no connects on the GMCH. For the GMCH, this includes
SDQ[71:64], SDQS8, SDM8 and the two differential clock pairs that are not routed to the SO-DIMMs.
The 855GM/GME chipset GMCH provides the capability to enable and disable the CS/CKE control and
SCK signals to unpopulated SO-DIMMs to save power. Although DDR SO-DIMM connectors may
provide motherboard lands for three clock pairs, non-ECC SO-DIMMs only require two pairs.
The GMCH provides some flexibility on how the SCK clock pairs, control signals and CPC signals are
assigned to the SO-DIMMs, provided that BIOS initialization of memory matches the hardware
configuration. Two examples are listed below. Refer to the Intel(R) 855GM/GME Memory Reference
Code for more details.
®
Intel
855GM/855GME Chipset Platform Design Guide
System Memory Design Guidelines (DDR-SDRAM) for SO-DIMM configuration
115
Advertisement
Table of Contents
