Pch Endpoint Pcie Configuration; Intel ® Communications Chipset 89Xx Series Skus; Intel ® Xeon ® Processor E3-1125C Pcie Port0 Configuration; Intel ® Xeon ® Processor E3-1125C Pcie Lane Reversal - Intel Xeon E3-1125C User Manual

Introduction—Crystal Forest
Ref Des
Location
J4B1
J4B2
J3B1
J2B2
J2B1
PCI Express Hot-Plug is not supported.
1.12

PCH EndPoint PCIe Configuration

This section provides details on how to configure the PCIe for the supported Intel
Communications Chipset 89xx Series SKU.
®
Table 7. Intel Communications Chipset 89xx Series SKUs
®
Intel
The PCH EndPoint can operate as a x4, x8, or x16 depending on the SKU and
population of the headers below.
®
Table 8. Intel Xeon
J6F6
CFG<6>
Bit
1
1
0
0
The Intel
Lane Reversal and Polarity Inversion must be done at a port level on the processor
part (as outlined below).
®
Table 9. Intel Xeon
PCIe x16 - Lane Reversal
PCIe x16 - No Lane Reversal (Default)
PCIe x4 - Lane Reversal
PCIe x4 - No Lane Reversal (Default)
In addition to the above headers, additional headers affect the PCIe training at boot-
up.
October 2012
Order No.: 328009-001US
Description
PCI Express Slot 2
PCI Express Slot 3 PCH Root Complex (2.5 GT/
s Max)
PCI Express Slot 4
PCI Express Slot 5
PCI Express Slot 6
Communications Chipset 89xx Series
SKU
#3
®
Processor E3-1125C PCIe Port0 Configuration
J6E4 Intel
CFG<5>
Bit
1 x16
0 x8 & x8
1 Reserved
0 x8, x4 & x4
®
Communications Chipset 89xx Series EndPoint also supports lane reversal.
®
Processor E3-1125C PCIe Lane Reversal
® ®
Intel Xeon Processor E3-1125C with Intel
The PCI Express Ports comply with PCI
Express* Base Specification, Rev. 1.0a. All
PCI Express slots (3, 4, 5, 6) employ
physical x8 connectors regardless of
whether they are x1, x4, or x8. This
enables use of x8 cards even if the actual
bandwidth and functionality is less.
® ®
Xeon Processor E3-1125C Port Bifurication
J6E5 - Closed
J6E5 - Open
J6E6 - Closed
J6E6 - Open
®
Communications Chipset 8910 Development Kit
Notes
®
PCIe Width
x8
Jumper
User Guide
15