Interrupt Conditions; Interrupts That Occur For Fcan Controller; Interrupts That Occur For Global Can Interface - NEC Renesas V850/SC1 User Manual

19.15 Interrupt Conditions

19.15.1 Interrupts that occur for FCAN controller

When interrupts are enabled (condition <1>: the M_CTRLm register's IE bit = 1, conditions other than <1>: C_IE
register's interrupt flags = 1), interrupts will occur under the following conditions (m = 00 to 31).
<1> Message-related operation has succeeded
• When a message has been received in the receive message buffer
• When a remote frame has been received in the transmit message buffer
(only when auto acknowledge mode has not been set, i.e., when the M_CTRLm register's RMDE0 bit = 0)
• When a message has been transmitted from the transmit message buffer
<2> When a CAN bus error has been detected
• Bit error
• Bit stuff error
• Form error
• CRC error
• ACK error
<3> When the CAN bus mode has been changed
• Error passive status elapsed while FCAN was transmitting
• Bus off status was set while FCAN was transmitting
• Error passive status elapsed while FCAN was receiving
<4> Internal error
• Overrun error

19.15.2 Interrupts that occur for global CAN interface

Interrupts occur for the global CAN interface under the following conditions.
<1> Interrupt source generated at GINT1 (GINTP register)
• Access to unused area in the CAN module
• When clearing (0) the GOM bit is attempted with the EFSD bit of the CGST register = 0, when there is
even one CAN module not initialized (INIT bit of CnCTRL register = 0)
<2> Interrupt source generated at GINT2 (CGINTP register)
• Write access to the CAN module register (register with a name starting with "Cn" (n = 1, 2)), when the
GOM bit of the CGST register = 0
• Write access to a temporary buffer area when the GOM bit of the CGST register = 1
CHAPTER 19 FCAN CONTROLLER (V850/SC3)
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