Operation Timing When Using Busy Control Option (Busy0 = 0) - NEC mPD780208 Subseries User Manual

Figure 14-19. Operation Timing When Using Busy Control Option (BUSY0 = 0)
SCK1
SO1 D7 D6 D5 D4 D3 D2 D1 D0
SI1 D7 D6 D5 D4 D3 D2 D1 D0
BUSY
CSIIF1
TRF
Caution When TRF is cleared, the SO1 pin becomes low level.
Remark CSIIF1: Interrupt request flag
TRF:
When the busy signal becomes inactive, the wait is cleared. If the sampled busy signal is inactive,
transmission/reception of the next 8-bit data is started at the falling edge of the next serial clock.
Note that, because the busy signal is asynchronous to the serial clock, it takes the master device
up to 1 clock to sample the busy signal even if the slave device has made the busy signal inactive.
In addition, it takes 0.5 clock until data transfer is started after the signal has been sampled.
To clear the wait, therefore, it is necessary for the slave device to keep the busy signal inactive for
at least 1.5 clocks.
Figure 14-20 shows the timing of the busy signal and wait clearance. In Figure 14-20, the busy signal
becomes active as soon as transmission/reception has started.
Figure 14-20. Busy Signal and Clearing Wait (BUSY0 = 0)
SCK1
SO1
D7 D6 D5 D4 D3 D2 D1 D0
SI1 D7 D6 D5 D4 D3 D2 D1 D0
BUSY
(active high)
CHAPTER 14 SERIAL INTERFACE CHANNEL 1
Wait
Bit 3 of the automatic data transmit/receive control register (ADTC)
If busy signal becomes
inactive immediately after
it has been sampled.
User's Manual U11302EJ4V0UM
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Busy input clear
Busy input valid
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1.5 clocks (min.)
Wait
Busy input clear
Busy input valid
293