Operation Of Watchdog Timer; Watchdog Timer Operation When "Low-Speed Ring-Osc Cannot Be Stopped" Is Selected By Option Byte - NEC 78K0S/KA1+ Preliminary User's Manual

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9.4

Operation of Watchdog Timer

9.4.1
The operation clock of watchdog timer is fixed to low-speed Ring-OSC.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
The following shows the watchdog timer operation after reset release.
1. The status after reset release is as follows.
• Operation clock: Low-speed Ring-OSC clock
• Cycle: f
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• Counting starts
2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
instruction
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1.
Caution In this mode, operation of the watchdog timer cannot be stopped even during STOP instruction
A status transition diagram is shown below

Watchdog timer operation when "low-speed Ring-OSC cannot be stopped" is selected by option byte

18
/2 (1.09 seconds: At operation with f
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Notes 1, 2
.
The operation clock (low-speed Ring-OSC clock) cannot be changed. If any value is written to bits 3
and 4 (WDCS3, WDCS4) of WDTM, it is ignored.
2. As soon as WDTM is written, the counter of the watchdog timer is cleared.
execution. For 8-bit timer H1 (TMH1), a division of the low-speed Ring-OSC clock can be
selected as the count source, so clear the watchdog timer using the interrupt request of TMH1
before the watchdog timer overflows after STOP instruction execution. If this processing is not
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
CHAPTER 9 WATCHDOG TIMER
= 240 kHz (TYP.))
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