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9.4 Operation of Watchdog Timer
9.4.1 Watchdog timer operation when "Ring-OSC cannot be stopped" is selected by option byte
The operation clock of watchdog timer is fixed to Ring-OSC.
After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) of
the watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.
The following shows the watchdog timer operation after reset release.
1.
The status after reset release is as follows.
• Operation clock: Ring-OSC clock
• Cycle: f
18
/2
(1.09 seconds: At operation with f
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• Counting starts
2.
The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulation
Notes 1, 2
instruction
.
• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)
3.
After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.
Notes 1.
The operation clock (Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4
(WDCS3, WDCS4) of WDTM, it is ignored.
2.
As soon as WDTM is written, the counter of the watchdog timer is cleared.
Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOP
instruction execution. For 8-bit timer H1 (TMH1), a division of the Ring-OSC can be selected as
the count source, so after STOP instruction execution, clear the watchdog timer using the
interrupt request of TMH1 before the watchdog timer overflows.
performed, an internal reset signal is generated when the watchdog timer overflows after STOP
instruction execution.
CHAPTER 9 WATCHDOG TIMER
= 240 kHz (TYP.))
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Preliminary User's Manual U16846EJ1V0UD
If this processing is not
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