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FFFFH
16-bit counter
0000H
TP0CE bit
External trigger input
(TIP00 pin input)
TP0CCR0 register
INTTP0CC0 signal
TOP00 pin output
(software trigger)
TP0CCR1 register
INTTP0CC1 signal
TOP01 pin output
When the TP0CE bit is set to 1, 16-bit timer/event counter P waits for a trigger. When the trigger is generated, the
16-bit counter is cleared from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOP01 pin.
After the one-shot pulse is output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a
trigger is generated again while the one-shot pulse is being output, it is ignored.
The output delay period and active level width of the one-shot pulse can be calculated as follows.
Output delay period = (Set value of TP0CCR1 register) × Count clock cycle
Active level width = (Set value of TP0CCR0 register − Set value of TP0CCR1 register + 1) × Count clock cycle
The compare match interrupt request signal INTTP0CC0 is generated when the 16-bit counter counts after its
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal INTTP0CC1
is generated when the count value of the 16-bit counter matches the value of the CCR1 buffer register.
The valid edge of an external trigger input or setting the software trigger (TP0CTL1.TP0EST bit) to 1 is used as the
trigger.
182
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 6-21. Basic Timing in One-Shot Pulse Output Mode
D
0
D
1
Delay
Active
(D
)
level width
1
− D
(D
+ 1)
0
1
User's Manual U16896EJ2V0UD
D
0
D
D
1
1
D
0
D
1
Delay
Active
Delay
(D
)
level width
(D
)
1
1
− D
(D
+ 1)
0
1
D
0
Active
level width
− D
(D
+ 1)
0
1
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