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(2) Operation timing in free-running timer mode
(a) Interval operation with compare register
When 16-bit timer/event counter P is used as an interval timer with the TP0CCRa register used as a
compare register, software processing is necessary for setting a comparison value to generate the next
interrupt request signal each time the INTTP0CCa signal has been detected.
FFFFH
16-bit counter
0000H
TP0CE bit
TP0CCR0 register
INTTP0CC0 signal
TOP00 pin output
TP0CCR1 register
INTTP0CC1 signal
TOP01 pin output
When performing an interval operation in the free-running timer mode, two intervals can be set with one
channel.
To perform the interval operation, the value of the corresponding TP0CCRa register must be re-set in the
interrupt servicing that is executed when the INTTP0CCa signal is detected.
The set value for re-setting the TP0CCRa register can be calculated by the following expression, where
"D
" is the interval period.
a
Compare register default value: D
Value set to compare register second and subsequent time: Previous set value + D
(If the calculation result is greater than FFFFH, subtract 10000H from the result and set this value to the
register.)
Remark
a = 0, 1
206
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
D
10
D
00
D
D
D
00
Interval period
Interval period
(D
+ 1)
(10000H +
00
− D
D
)
01
00
D
10
Interval period
Interval period
(D
+ 1)
(10000H +
10
D
11
− 1
a
User's Manual U16896EJ2V0UD
D
02
D
D
11
03
D
12
01
D
D
01
02
03
Interval period
Interval period
Interval period
− D
(D
)
(10000H +
(10000H +
02
01
− D
D
)
D
03
02
04
D
D
11
12
Interval period
Interval period
(10000H +
(10000H +
− D
− D
− D
)
D
)
D
10
12
11
13
D
04
D
13
D
D
04
05
− D
)
03
D
D
13
14
)
12
a
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