NEC V850ES/KE1+ User Manual page 594

RESET signal
f
X
Internal
reset signal
(active low)
<1> Digital noise is eliminated when the RNZC.RNZSEL bit = 1.
<2> The RESET pin is always sampled at the rising edge of the sampling clock (f
<3> If the RESET pin goes low and is detected as low over the entire sampling timing, it is detected
as an internal reset signal. Because the analog noise eliminator is activated after digital noise
has been eliminated, the internal reset signal is detected after analog delay.
<4> When the internal reset signal is detected, the RNZC register is initialized, so only the analog
noise eliminator can be selected.
(b) Operation when sampling clock is stopped
If the sampling clock (f
signal is not received. Therefore, only the analog noise eliminator is automatically selected.
Only the analog noise eliminator is automatically selected during the following periods.
• In STOP mode:
Setting of STOP mode → Period to time set by the OSTS register that elapses after the STOP mode is
released (by a source other than reset)
• In subclock operation mode:
Setting of subclock operation mode (PCC.CLS bit = 0 → 1) → Period until the main clock operation
mode (CLS bit = 1 → 0) is restored
(c) Digital noise elimination width
The digital noise elimination width (t
number of samplings.
Digital Noise Elimination Width (t
T = 10 MHz, N = 20
< (N−1)T
t t
WRSL WRSL
(N−1)T < t < NT
1.9
WRSL
NT ≤ t
2.0
WRSL
Remark The noise on the RESET pin is eliminated by a value that takes the value shown in this table and the
analog delay value into consideration.
594
CHAPTER 20 RESET FUNCTION
Figure 20-4. Sampling Operation Timing (20 Times)
1 2 19 20
Digital noise
Analog
elimination delay
) stops when the digital + analog noise eliminator is selected, input to the RESET
X
) is as follows where T is the sampling clock period and N is the
WRSL
Table 20-2. Digital Noise Elimination Width of RESET Pin
)
WRSL
T = 5 MHz, N = 10
μ
< 1.9 < 1.8
s t
WRSL
μ μ μ
s ≤ t s ≤ t
< 2.0
s 1.8
WRSL
μ μ
s ≤ t s ≤ t
2.0
WRSL
User's Manual U16896EJ2V0UD
Oscillation stabilization time count
Analog
Period set by OSTS register
delay
μ
s Eliminated as noise
μ
< 2.0
s May be eliminated as noise or detected as reset
WRSL
Detected as reset
WRSL
).
X
Operation