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(6) TMP0 option register 0 (TP0OPT0)
The TP0OPT0 register is an 8-bit register used to set the capture/compare operation and detect an overflow.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
After reset: 00H
TP0OPT0
Cautions 1. Rewrite the TP0CCS1 and TP0CCS0 bits when the TP0CE
144
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
R/W
Address: FFFFF5A5H
6
5
7
0
0
TP0CCS1 TP0CCS0
TP0CCS1
TP0CCR1 register capture/compare selection
0
Compare register selected
1
Capture register selected
The TP0CCS1 bit setting is valid only in the free-running timer mode.
TP0CCS0
TP0CCR0 register capture/compare selection
0
Compare register selected
1
Capture register selected
The TP0CCS0 bit setting is valid only in the free-running timer mode.
TP0OVF
Set (1)
Overflow occurred
Reset (0)
TP0OVF bit 0 written or TP0CTL0.TP0CE bit = 0
• The TP0OVF bit is set when the 16-bit counter count value overflows from FFFFH
to 0000H in the free-running timer mode or the pulse width measurement mode.
• An interrupt request signal (INTTP0OV) is generated at the same time that the
TP0OVF bit is set to 1. The INTTP0OV signal is not generated in modes other
than the free-running timer mode and the pulse width measurement mode.
• The TP0OVF bit is not cleared even when the TP0OVF bit or the TP0OPT0
register is read when the TP0OVF bit = 1.
• The TP0OVF bit can be both read and written, but the TP0OVF bit cannot be set
to 1 by software. Writing 1 has no influence on the operation of TMP0.
bit = 0. (The same value can be written when the TP0CE
bit = 1.) If rewriting was mistakenly performed, clear the
TP0CE bit to 0 and then set the bits again.
2. Be sure to clear bits 1 to 3, 6, and 7 to "0".
User's Manual U16896EJ2V0UD
4
3
2
0
0
TMP0 overflow detection flag
1
<0>
0
TP0OVF
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