NEC V850ES/KE1+ User Manual page 456

32-bit single-chip microcontrollers
Table of Contents

Advertisement

(4) Cautions
To continue continuous transfers, it is necessary to either read the SIRBn register or write to the SOTBn
register during the transfer reservation period.
If access is performed to the SIRBn register or the SOTBn register when the transfer reservation period is
over, the following occurs.
(i) In case of conflict between transfer request clear and register access
Since transfer request clear has higher priority, the next transfer request is ignored. Therefore, transfer is
interrupted, and normal data transfer cannot be performed.
Figure 15-7. Transfer Request Clear and Register Access Conflict
SCK0n
(I/O)
INTCSI0n
signal
rq_clr
Reg_R/W
Remarks 1. rq_clr:
Reg_R/W: Internal signal. This signal indicates that the SIRBn/SIRBnL register read or the
2. n = 0, 1
456
CHAPTER 15 CLOCKED SERIAL INTERFACE 0 (CSI0)
Transfer reservation period
Internal signal. Transfer request clear signal.
SOTBn/SOTBnL register write was performed.
User's Manual U16896EJ2V0UD

Advertisement

Table of Contents
loading

This manual is also suitable for:

?pd70f3302?pd703302?pd70f3302y?pd703302y

Table of Contents