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To control carrier pulse output during count operation, the TMCYCn.NRZn and TMCYCn.NRZBn bits have a
master and slave bit configuration. The NRZn bit is read-only while the NRZBn bit can be read and written.
The INTTM5n signal is synchronized with the 8-bit timer Hn clock and output as the INTTM5Hn signal. The
INTTM5Hn signal becomes the data transfer signal of the NRZn bit and the value of the NRZBn bit is
transferred to the NRZn bit. The transfer timing from the NRZBn bit to the NRZn bit is as follows.
8-bit timer Hn count clock
<1> The INTTM5n signal is synchronized with the count clock of 8-bit timer Hn and is output as the
INTTM5Hn signal.
<2> The value of the NRZBn bit is transferred to the NRZn bit at the second clock from the rising edge of
the INTTM5Hn signal.
<3> Write the next value to the NRZBn bit in the interrupt servicing programming that has been started by
<R>
the INTTM5Hn interrupt or after timing has been checked by polling the interrupt request flag. Write
data to count the next time to the CR5n register.
Cautions 1. Do not rewrite the NRZBn bit again until at least the second clock after it has been
2. When using 8-bit timer/event counter 5n in the carrier generator mode, an interrupt
Remark n = 0, 1
330
CHAPTER 9 8-BIT TIMER H
Figure 9-6. Transfer Timing
TMHEn
INTTM5n
INTTM5Hn
<1>
0
NRZn
NRZBn
RMCn
rewritten, or else transfer from the NRZBn bit to the NRZn bit is not guaranteed.
occurs at the timing of <1>. An interrupt occurs at a different timing when it is used
in other than the carrier generator mode.
User's Manual U16896EJ2V0UD
1
<2>
1
0
<3>
0
1
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