NEC V850ES/KE1+ User Manual page 545

32-bit single-chip microcontrollers
Table of Contents

Advertisement

CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Main routine
EI
Interrupt request j
Interrupt request i
(level 2)
Interrupt request k
Interrupt request l
Interrupt request n
(level 2)
Interrupt request o
Interrupt request p
(level 3)
Interrupt request s
(level 1)
Notes 1. Lower default priority
2. Higher default priority
Figure 17-6. Example of Interrupt Nesting (2/2)
Servicing of i
EI
(level 3)
(level 1)
Servicing of j
Servicing of l
Interrupt request m
(level 3)
(level 1)
Servicing of n
Servicing of m
Servicing of o
Servicing of p
EI
EI
Interrupt request q
(level 2)
Interrupt request r
(level 1)
Servicing of s
Interrupt request t
Note 1
(level 2)
Interrupt request u
Note 2
(level 2)
Servicing of u
Servicing of t
User's Manual U16896EJ2V0UD
Servicing of k
Interrupt request j is held pending because its
priority is lower than that of i. k that occurs after j is
acknowledged because it has the higher priority.
Interrupt requests m and n are held pending
because servicing of l is performed in the interrupt
disabled status.
Pending interrupt requests are acknowledged after
servicing of interrupt request l.
At this time, interrupt request n is acknowledged
first even though m has occurred first because the
priority of n is higher than that of m.
Servicing of q
Servicing of r
EI
EI
(level 0)
If levels 3 to 0 are acknowledged
Pending interrupt requests t and u are
acknowledged after processing of s.
Because the priorities of t and u are the same, u is
acknowledged first because it has the higher
default priority, regardless of the order in which the
interrupt requests have been generated.
545

Advertisement

Table of Contents
loading

This manual is also suitable for:

?pd70f3302?pd703302?pd70f3302y?pd703302y

Table of Contents