Table of Contents
Advertisement
Figure 6-22. Setting of Registers in One-Shot Pulse Output Mode (2/2)
(d) TMP0 I/O control register 2 (TP0IOC2)
TP0IOC2
0
0
(e) TMP0 counter read buffer register (TP0CNT)
The value of the 16-bit counter can be read by reading the TP0CNT register.
(f) TMP0 capture/compare registers 0 and 1 (TP0CCR0 and TP0CCR1)
If D
is set to the TP0CCR0 register and D
0
delay period of the one-shot pulse are as follows.
Active level width = (D
Output delay period = D
Remark
TMP0 I/O control register 1 (TP0IOC1) and TMP0 option register 0 (TP0OPT0) are not used
in the one-shot pulse output mode.
184
CHAPTER 6 16-BIT TIMER/EVENT COUNTER P (TMP)
TP0EES1
0
0
0/1
to the TP0CCR1 register, the active level width and output
1
− D
+ 1) × Count clock cycle
1
0
× Count clock cycle
1
User's Manual U16896EJ2V0UD
TP0EES0 TP0ETS1 TP0ETS0
0/1
0/1
0/1
Select valid edge of
external trigger input
Select valid edge of
external event count input
Advertisement
Table of Contents
