NEC V850ES/KE1+ User Manual page 544

32-bit single-chip microcontrollers
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CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
Main routine
Interrupt request a
(level 3)
Interrupt request c
(level 3)
Interrupt request e
(level 2)
Interrupt request g
(level 1)
Caution The values of EIPC and EIPSW must be saved before executing multiple interrupts.
Remarks 1. a to u in the figure are the names of interrupt request signals shown for the sake of explanation.
2. The default priority in the figure indicates the relative priority between two interrupt request signals.
544
Figure 17-6. Example of Interrupt Nesting (1/2)
Servicing of a
EI
EI
Interrupt request b
(level 2)
Servicing of c
Interrupt request d
(level 2)
Servicing of d
Servicing of e
EI
Interrupt request f
(level 3)
Servicing of f
Servicing of g
EI
Interrupt request h
(level 1)
Servicing of h
User's Manual U16896EJ2V0UD
Servicing of b
Interrupt request b is acknowledged
because the priority of b is higher than
that of a and interrupts are enabled.
Although the priority of interrupt request
d is higher than that of c, d is held pending
because interrupts are disabled.
Interrupt request f is held pending even if
interrupts are enabled because its priority
is lower than that of e.
Interrupt request h is held pending even if
interrupts are enabled because its priority
is the same as that of g.

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