NEC V850ES/KE1+ User Manual page 556

CHAPTER 17 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(1) External interrupt rising and falling edge specification registers 0 (INTR0, INTF0)
These are 8-bit registers that specify detection of the rising and falling edges of the NMI and INTP0 to INTP3
pins.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When switching to the port function from the external interrupt function (alternate function),
edge detection may be performed. Therefore, set the port mode after setting the INTF0n and
INTR0n bits = 00.
After reset: 00H
INTR0
INTF0
Remark
Table 17-3. NMI and INTP0 to INTP3 Pins Valid Edge Specification
INTF0n
0
0
1
1
Remark n = 2:
n = 3 to 6: Control of INTP0 to INTP3 pins
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R/W Address: INTR0 FFFFFC20H, INTF0 FFFFFC00H
0 INTR06 INTR05 INTR04
INTP3 INTP2 INTP1
0 INTF06 INTF05 INTF04
INTP3 INTP2 INTP1
For specification of the valid edge, refer to Table 17-3.
INTR0n
0 No edge detection
1 Rising edge
0 Falling edge
1 Both edges
Control of NMI pin
User's Manual U16896EJ2V0UD
INTR03 INTR02
INTP0 NMI
INTF03 INTF02
INTP0 NMI
Valid edge specification (n = 2 to 6)
0 0
0 0