NEC V850ES/KE1+ User Manual page 583

32-bit single-chip microcontrollers
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(2) Releasing STOP mode by reset
The same operation as the normal reset operation is performed.
Item
CPU
ROM correction
Main clock oscillator
Subclock oscillator
Internal oscillator (f
Interrupt controller
16-bit timer (TMP0)
16-bit timer (TM01)
8-bit timers (TM50, TM51)
Timer H (TMH0)
Timer H (TMH1)
Watch timer
Watchdog timer 1
Watchdog timer 2
Serial interface
Key interrupt function
A/D converter
Real-time output
<R>
Clock monitor (CLM)
Power-on-clear (POC)
Low-voltage detection (LVI)
Port function
Internal data
Notes 1.
Only in the
2.
Set the ADM.ADCS and ADM.ADCS2 bits to 00B.
<R>
Remark m = 0, 1
CHAPTER 19 STANDBY FUNCTION
Table 19-7. Operation Status in STOP Mode
Setting of STOP Mode
Stops operation
Stops operation
Oscillation stops
)
Operable
R
Stops operation
Stops operation
Stops operation
Operable when TI5m is selected as count
clock
Stops operation
Operable when f
Stops operation
Stops operation
Operable when f
clock
CSI00, CSI01
Operable when SCK0m input clock is selected as operation clock
2
Note 1
I
C0
Stops operation
UART0
Operable when ASCK0 is selected as count clock
UART1
Stops operation
Operable
Stops operation
Operable when INTTM5m is selected as real-time output trigger and TM5m is enabled in
STOP mode.
However, the RTBH0 and RTBL0 registers cannot be updated because the CPU is
stopped.
Stops operation
Operable
Operable
Retains status before STOP mode was set.
The CPU registers, statuses, data, and all other internal data such as the contents of the
internal RAM are retained as they were before the STOP mode was set.
μ
PD703302Y, 70F3302Y
When CPU Is Operating with Main Clock
When Subclock Is Not Used
/2048 is selected as count clock
R
/8 is selected as count
R
Note 2
User's Manual U16896EJ2V0UD
When Subclock Is Used
Oscillation enabled
Operable when INTWT is selected as
count clock and f
is selected as count
XT
clock of WT
Operable when TI5m is selected as count
clock or when INTTM010 is selected as
count clock and TM01 is enabled in STOP
mode
Operable when f
is selected as count clock
XT
Operable
583

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