NEC V850ES/KE1+ User Manual page 130

(a) Example of setting main clock operation → subclock operation
<1> CK3 bit ← 1:
<2> Subclock operation: Read the CLS bit to check if subclock operation has started. It takes the
<3> MCK bit ← 1:
Cautions 1. When stopping the main clock, stop the PLL.
2. If the following conditions are not satisfied, change the CK2 to CK0 bits so that the
conditions are satisfied, then change to the subclock operation mode.
Remark Internal system clock (f
[Description example]
<1> _SET_SUB_RUN :
st.b
set1
<2> _CHECK_CLS :
tst1
bz
<3> _STOP_MAIN_CLOCK :
st.b
set1
Remark The above description is an example. Note with caution that the CLS bit is read in a closed
loop in <2>.
130
CHAPTER 5 CLOCK GENERATION FUNCTION
Use of a bit manipulation instruction is recommended. Do not change the CK2
to CK0 bits.
following time after the CK3 bit is set until subclock operation is started.
Max.: 1/f (1/subclock frequency)
XT
Set the MCK bit to 1 only when stopping the main clock.
Internal system clock (f
CLK
): Clock generated from the main clock (f
CLK
CK0 bits
r0, PRCMD[r0]
3, PCC[r0]
4, PCC[r0]
_CHECK_CLS
r0, PRCMD[r0]
6, PCC[r0]
User's Manual U16896EJ2V0UD
: 32.768 kHz) × 4
) > Subclock (f
XT
-- CK3 bit ← 1
-- Wait until subclock operation starts.
-- MCK bit ← 1, main clock is stopped
) by setting the CK2 to
XX